Table 9-36, Table 9-37, Tag register format for reads, with parity -29 – ARM Cortex R4F User Manual
Page 262: Table 9-38, Tag register format for reads, with ecc -29
Level Two Interface
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
9-29
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Tag RAM access
The following tables show the data formats for tag RAM accesses:
•
Table 9-36 shows the format for read accesses when neither parity nor ECC is
implemented
•
Table 9-37 shows the format for read accesses when parity is implemented
•
Table 9-38 shows the format for read accesses when ECC is implemented
•
Table 9-39 on page 9-30 shows the format for write accesses when neither parity nor ECC
is implemented
•
Table 9-40 on page 9-30 shows the format for write accesses when parity is implemented
•
Table 9-41 on page 9-30 shows the format for write accesses when ECC is implemented.
Table 9-36 Tag register format for reads, no parity or ECC
Data bit
Description
[63:55]
Not used, read-as-zero
[54]
Valid, way 2/3
[53:32]
Tag value, way 2/3
[31:23]
Not used, read-as-zero
[22]
Valid, way 0/1
[21:0]
Tag value, way 0/1
Table 9-37 Tag register format for reads, with parity
Data bit
Description
[63:56]
Not used, read-as-zero
[55]
Parity, way 2/3
[54]
Valid, way 2/3
[53:32]
Tag value, way 2/3
[31:24]
Not used, read-as-zero
[23]
Parity, way 0/1
[22]
Valid, way 0/1
[21:0]
Tag value, way 0/1
Table 9-38 Tag register format for reads, with ECC
Data bit
Description
[63:62]
Not used, read-as-zero
[61:55]
ECC, way 2/3
[54]
Valid, way 2/3
[53:32]
Tag value, way 2/3