ARM Cortex R4F - Manual (Page 448)

Glossary
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Clean A cache line that has not been modified while it is in the cache is said to be clean. To clean a
cache is to write dirty cache entries into main memory. If a cache line is clean, it is not written
on a cache miss because the next level of memory contains the same data as the cache.
See also Dirty.
Clock gating Gating a clock signal for a macrocell with a control signal (such as PWRDOWN) and using the
modified clock that results to control the operating state of the macrocell.
Clocks Per Instruction (CPI)
See Cycles Per Instruction (CPI).
Coherency See Memory coherency.
Cold reset Also known as power-on reset. Starting the processor by turning power on. Turning power off
and then back on again clears main memory and many internal settings. Some program failures
can lock up the processor and require a cold reset to enable the system to be used again. In other
cases, only a warm reset is required.
See also Warm reset.
Communications channel
Software running on an ARM processor uses this to communicate with an external host through
the debug interface. It can also be called the Debug Communications Channel. It is
architecture-defined. See the ARM Architecture Reference Manual and your product technical
reference manual for specific information.
Condition field A 4-bit field in an instruction that is used to specify a condition under which the instruction can
execute.
Conditional execution
If the condition code flags indicate that the corresponding condition is true when the instruction
starts executing, it executes normally. Otherwise, the instruction does nothing.
Context The environment that each process operates in for a multitasking operating system. In ARM
processors, this is limited to mean the physical address range that it can access in memory and
the associated memory access permissions.
See also Fast context switch.
Control bits The bottom eight bits of a Program Status Register (PSR). The control bits change when an
exception arises and can be altered by software only when the processor is in a Privileged mode.
Coprocessor A processor that supplements the main processor. It carries out additional functions that the
main processor cannot perform. Usually used for floating-point math calculations, signal
processing, or memory management.
Copy back See Write-back.
Core module In the context of an ARM Integrator, a core module is an add-on development board that
contains an ARM processor and local memory. Core modules can run standalone, or can be
stacked onto Integrator motherboards.
Core reset See Warm reset.
CPI See Cycles per instruction.
CPSR See Current Program Status Register.
Current Program Status Register (CPSR)
The register that holds the current operating processor status.