ARM Cortex R4F - Manual (Page 59)

Programmer’s Model
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-13
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Note
GE bit is 1 if A op B ≥ C, otherwise 0.
The SEL instruction uses GE[3:0] to select which source register supplies each byte of its result.
Note
• For unsigned operations, the usual ARM rules determine the GE bits for carries out of
unsigned additions and subtractions, and so are carry-out bits.
• For signed operations, the rules for setting the GE bits are chosen so that they have the
same sort of greater than or equal functionality as for unsigned operations.
2.7.7 The E bit
ARM and Thumb instructions are provided to set and clear the E bit. The E bit controls
load/store endianness. See the ARM Architecture Reference Manual for information on where
the E bit is used.
Architecture versions prior to ARMv6 specify this bit as SBZ. This ensures no endianness
reversal on loads or stores.
2.7.8 The A bit
The A bit is set automatically. It disables imprecise Data Aborts. For more information on how
to use the A bit, see Imprecise abort masking on page 2-23.
2.7.9 The I and F bits
The I and F bits are the interrupt disable bits:
•
when the I bit is set, IRQ interrupts are disabled
• when the F bit is set, FIQ interrupts are disabled.
Software can use MSR , CPS , MOVS pc , SUBS pc , LDM ..,{..pc}^ , or RFE instructions to change the
values of the I and F bits.
When NMFIs are enabled, updates to the F bit are restricted. For more information see
Non-maskable fast interrupts on page 2-19.
2.7.10 The T bit
The T bit reflects the instruction set state:
•
when the T bit is set, the processor executes in Thumb state
• when the T bit is clear, the processor executes in ARM state.
Note
Never use an
MSR
instruction to force a change to the state of the T bit in the CPSR. The processor
ignores any attempt to modify the T bit using an
MSR
instruction.