ARM Cortex R4F - Manual (Page 127)

System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-43
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[16] DOOFMACS Out-of-order FMACS control. c
0 = Enabled. This is the reset value.
1 = Disabled.
[15:14] Reserved SBZ.
[13] IXC Floating-point inexact exception output mask. c
0 = Mask floating-point inexact exception output. The output FPIXC is forced to zero. This
is the reset value.
1 = Propagate floating point inexact exception flag
FPSCR.IXC
to output FPIXC.
[12] OFC Floating-point overflow exception output mask. c
0 = Mask floating-point overflow exception output. The output FPOFC is forced to zero. This
is the reset value.
1 = Propagate floating-point overflow exception flag
FPSCR.OFC to output FPOFC.
[11] UFC Floating-point underflow exception output mask. c
0 = Mask floating-point underflow exception output. The output FPUFC is forced to zero.
This is the reset value.
1 = Propagate floating-point underflow exception flag
FPSCR.UFC
to output FPUFC.
[10] IOC Floating-point invalid operation exception output mask. c
0 = Mask floating-point invalid operation exception output. The output FPIOC is forced to
zero. This is the reset value.
1 = Propagate floating-point invalid operation exception flag
FPSCR.IOC to output FPIOC.
[9] DZC Floating-point divide-by-zero exception output mask. c
0 = Mask floating-point divide-by-zero exception output. The output FPDZC is forced to
zero. This is the reset value.
1 = Propagate floating-point divide-by-zero exception flag
FPSCR.DZC
to output FPDZC.
[8] IDC Floating-point input denormal exception output mask. c
0 = Mask floating-point input denormal exception output. The output FPIDC is forced to zero.
This is the reset value.
1 = Propagate floating-point input denormal exception flag
FPSCR.IDC to output FPIDC.
[7:4} Reserved SBZ.
[3] BTCMECC Correction for internal ECC logic on BTCM ports. d
0 = Enabled. This is the reset value.
1 = Disabled.
Table 4-25 Secondary Auxiliary Control Register bit functions (continued)
Bits Field Function