ARM Cortex R4F - Manual (Page 244)

Level Two Interface
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-11
ID013010 Non-Confidential, Unrestricted Access
STRB
Table 9-8 shows the values of AWADDRM, AWBURSTM, AWSIZEM, and AWLENM for
an
STRB to Strongly Ordered or Device memory over the AXI master port.
STRH
Table 9-9 shows the values of AWADDRM, AWBURSTM, AWSIZEM, and AWLENM for
an
STRH
over the AXI master port to Strongly Ordered or Device memory.
Note
A store of a halfword to Strongly Ordered or Device memory addresses
0x1
,
0x3
,
0x5
, or
0x7
generates an alignment fault.
Table 9-8 STRB to Strongly Ordered or Device memory
Address[4:0] AWADDRM AWBURSTM AWSIZEM AWLENM WSTRBM
0x00 (byte 0) 0x00 Incr 8-bit 1 data transfer b00000001
0x01
(byte 1)
0x01
Incr 8-bit 1 data transfer b00000010
0x02 (byte 2) 0x02 Incr 8-bit 1 data transfer b00000100
0x03 (byte 3) 0x03 Incr 8-bit 1 data transfer b00001000
0x04
(byte 4)
0x04
Incr 8-bit 1 data transfer b00010000
0x05 (byte 5) 0x05 Incr 8-bit 1 data transfer b00100000
0x06 (byte 6) 0x06 Incr 8-bit 1 data transfer b01000000
0x07 (byte 7) 0x07 Incr 8-bit 1 data transfer b10000000
Table 9-9 STRH to Strongly Ordered or Device memory
Address[2:0] AWADDRM AWBURSTM AWSIZEM AWLENM WSTRBM
0x0 (halfword 0) 0x00 Incr 16-bit 1 data transfer b00000011
0x2 (halfword 1) 0x02 Incr 16-bit 1 data transfer b00001100
0x4
(halfword 2)
0x04
Incr 16-bit 1 data transfer b00110000
0x6 (halfword 3) 0x06 Incr 16-bit 1 data transfer b11000000