ARM Cortex R4F User Manual
Page 65
Programmer’s Model
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
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You can disable IRQ exceptions within a Privileged mode by setting the CPSR.I bit to b1. See
Program status registers on page 2-10. IRQ interrupts are automatically disabled when an IRQ
occurs, by setting the CPSR.I bit. You can use nested interrupts but it is up to you to save any
corruptible registers and to re-enable IRQs by clearing the CPSR.I bit.
Fast interrupt request
The Fast Interrupt Request (FIQ) reduces the execution time of the exception handler relative
to a normal interrupt. FIQ mode has eight private registers to reduce, or even remove the
requirement for register saving (minimizing the overhead of context switching).
An FIQ is externally generated by taking the nFIQ input signal LOW. You must ensure that the
nFIQ input is held LOW until the processor acknowledges the interrupt request from the
software handler.
Irrespective of whether exception entry is from ARM state or Thumb state, an FIQ handler
returns from the interrupt by executing:
SUBS PC, R14_fiq, #4
If Non-Maskable Fast Interrupts (NMFIs) are not enabled, you can mask FIQ exceptions by
setting the CPSR.F bit to b1. For more information see:
•
Program status registers on page 2-10
•
FIQ and IRQ interrupts are automatically masked by setting the CPSR.F and CPSR.I bits when
an FIQ occurs. You can use nested interrupts but it is up to you to save any corruptible registers
and to re-enable interrupts.
Non-maskable fast interrupts
When NMFI behavior is enabled, FIQ interrupts cannot be masked by software. Enabling NMFI
behavior ensures that when the FIQ mask, that is, the CPSR.F bit, has been cleared by the reset
handler, fast interrupts are always taken as quickly as possible, except during handling of a fast
interrupt. This makes the fast interrupt suitable for signaling critical events. NMFI behavior is
controlled by a configuration input signal CFGNMFI, that is asserted HIGH to enable NMFI
operation. There is no software control of NMFI.
Software can detect whether NMFI operation is enabled by reading the NMFI bit of the System
Control Register:
NMFI == 0 Software can mask FIQs by setting the CPSR.F bit to b1.
NMFI == 1 Software cannot mask FIQs.
For more information see c1, System Control Register on page 4-35.
When the NMFI bit in the System Control Register is b1:
•
an instruction writing b0 to the CPSR.F bit clears it to b0
•
an instruction writing b1 to the CPSR.F bit leaves it unchanged
•
the CPSR.F bit can be set to b1 only by an FIQ or reset exception entry.
Low interrupt latency
Low Interrupt Latency (LIL) is a set of behaviors that reduce the interrupt latency for the
processor, and is enabled by default. That is, the FI bit [21] in the System Control Register is
Read-as-One.