ARM Cortex R4F - Manual (Page 447)

Glossary
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. Glossary-6
ID013010 Non-Confidential, Unrestricted Access
Byte invariant In a byte-invariant system, the address of each byte of memory remains unchanged when
switching between little-endian and big-endian operation. When a data item larger than a byte
is loaded from or stored to memory, the bytes making up that data item are arranged into the
correct order depending on the endianness of the memory access. The ARM architecture
supports byte-invariant systems in ARMv6 and later versions. When byte-invariant support is
selected, unaligned halfword and word memory accesses are also supported. Multi-word
accesses are expected to be word-aligned.
See also Word-invariant.
Byte lane strobe An AXI signal, WSTRB, that is used for unaligned or mixed-endian data accesses to determine
which byte lanes are active in a transfer. One bit of WSTRB corresponds to eight bits of the data
bus.
Byte swizzling The reverse ordering of bytes in a word.
Cache A block of on-chip or off-chip fast access memory locations, situated between the processor and
main memory, used for storing and retrieving copies of often used instructions and/or data. This
is done to greatly increase the average speed of memory accesses and so improve processor
performance.
See also Cache terminology diagram on the last page of this glossary.
Cache contention When the number of frequently-used memory cache lines that use a particular cache set exceeds
the set-associativity of the cache. In this case, main memory activity increases and performance
decreases.
Cache hit A memory access that can be processed at high speed because the instruction or data that it
addresses is already held in the cache.
Cache line The basic unit of storage in a cache. It is always a power of two words in size (usually four or
eight words), and is required to be aligned to a suitable memory boundary.
See also Cache terminology diagram on the last page of this glossary.
Cache line index The number associated with each cache line in a cache set. Within each cache set, the cache lines
are numbered from 0 to (set associativity) -1.
See also Cache terminology diagram on the last page of this glossary.
Cache miss A memory access that cannot be processed at high speed because the instruction/data it
addresses is not in the cache and a main memory access is required.
Cache set A cache set is a group of cache lines (or blocks). A set contains all the ways that can be
addressed with the same index. The number of cache sets is always a power of two. All sets are
accessed in parallel during a cache look-up.
See also Cache terminology diagram on the last page of this glossary.
Cache set associativity
The maximum number of cache lines that can be held in a cache set.
See also Set-associative cache and Cache terminology diagram on the last page of this glossary.
Cache way A group of cache lines (or blocks). It is 2 to the power of the number of index bits in size.
See also Cache terminology diagram on the last page of this glossary.
Cast out See Victim.