ARM Cortex R4F - Manual (Page 268)

Power Control
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 10-3
ID013010 Non-Confidential, Unrestricted Access
10.2 Power management
The processor supports four levels of power management. This section describes:
•
Run mode
• Standby mode
• Dormant mode
• Shutdown mode
• Communication to the Power Management Controller on page 10-4.
10.2.1 Run mode
Run mode is the normal mode of operation where all of the functionality of the processor is
available.
10.2.2 Standby mode
Standby mode disables most of the clocks of the device, while keeping the design powered up.
This reduces the power drawn to the static leakage current, plus a tiny clock power overhead
required to enable the device to wake up from the Standby mode.
The transition from Standby mode to Run mode is caused by:
•
the arrival of an interrupt, whether masked or unmasked
• a debug request, whether debug is enabled or disabled
• a reset.
The debug request can be generated by an externally generated debug request, using the
EDBGRQ pin on the processor, or from a Debug Halt instruction issued to the processor
through the debug Advanced Peripheral Bus (APB).
Entry into Standby mode is performed by executing the Wait For Interrupt (
WFI
) instruction. To
ensure that the entry into the Standby mode does not affect the memory system, the
WFI
automatically performs a Data Synchronization Barrier operation. This ensures that all explicit
memory accesses occur in program order before the
WFI
has completed.
Systems using the VIC interface must ensure that the VIC is not masking any interrupts that are
required for restarting the processor when in this mode of operation.
When the processor clocks are stopped the STANDBYWFI signal is asserted to indicate that
the processor is in Standby mode.
When the processor is in Standby mode and the AXI slave interface receives a transaction, the
processor clocks are temporarily restarted and STANDBYWFI is deasserted to enable it to
service the transaction, but it does not return to Run mode.
10.2.3 Dormant mode
Dormant mode ensures that only the processor logic, but not the processor TCM and cache
RAMs, is powered down. In dormant mode, the processor state, apart from the cache and TCM
state, is stored to memory before entry into this mode, and restored after exit. For more
information on how to implement and use dormant mode in your design, contact ARM.
10.2.4 Shutdown mode
Shutdown mode has the entire device powered down, and you must externally save all state,
including cache and TCM state. The processor is returned to Run mode by asserting and
deasserting nRESET. When you perform state saving, you must ensure that interrupts are