ARM Cortex R4F - Manual (Page 161)

Prefetch Unit
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5.1 About the prefetch unit
The purpose of the PFU is to:
• perform speculative fetch of instructions ahead of the DPU by predicting the outcome of
branch instructions
• format instruction data in a way that aids the DPU in efficient implementation.
The PFU fetches instructions from the memory system under the control of the DPU, and the
internal coprocessors CP14 and CP15. In ARM state the memory system can supply up to two
instructions per cycle. In Thumb state the memory system can supply up to four instructions per
cycle.
The PFU buffers up to three instruction data fetches in its FIFO. There is an additional FIFO
between the PFU and the DPU that can normally buffer up to eight instructions. This reduces or
eliminates stall cycles after a branch instruction. This increases the performance of the
processor.
Program flow prediction occurs in the PFU by:
• predicting the outcome of conditional branches using the branch predictor and, for direct
branches, calculating their destination address using the offset encoded in the instruction
• predicting the destination of procedure returns using the return stack.
The DPU resolves the program flow predictions that the PFU makes.
The PFU fetches the instruction stream as dictated by:
•
the Program Counter
• the branch predictor
• procedure returns signaled by the return stack
• exceptions including aborts and interrupts signaled by the DPU
• correction of mispredicted branches as indicated by the DPU.