ARM Cortex R4F - Manual (Page 330)

Debug
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-61
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Example 11-10 shows the code for single-stepping off an instruction.
Example 11-10 Single-stepping off an instruction
SingleStepOff(uint32 address)
{
bkpt := FindUnusedBreakpointWithMismatchCapability();
SetComplexBreakpoint(bkpt, address, 4 << 20);
}
Note
In Example 11-10, the third parameter of
SetComplexBreakpoint()
indicates the value to set
BCR[22:20].
This method of single-stepping steps off the instruction that might not necessarily be the same
as stepping to the next instruction executed. In certain circumstances, the next instruction
executed might be the same instruction being stepped off.
The simplest example of this is a branch to a self instruction such as
(B .)
. In this case, the
wanted behavior is most likely to step off the branch to self because this is often used as a means
of waiting for an interrupt.
A more complex example is a return from function that returns to the same point. For example,
a simple recursive function might terminate with:
BL ThisFunction
POP {saved_registers, pc}
In this case, the POP instruction loads a link register that is saved at the start of the function, and
if that is the link register created by the
BL
instruction shown, it points back at the
POP
instruction.
Therefore, this single step code unwinds the entire call stack to the point of the original caller,
rather than stepping out a level at a time. It is not possible to single step this piece of code using
either the high-level or low-level stepping methods.
11.11.4 Debug state entry
On entry to debug state, the debugger can read the processor state, including all registers and
the PC, and determine the cause of the exception from the DSCR method-of-entry bits.
Example 11-11 shows the code for entry to debug state.
Example 11-11 Entering debug state
OnEntryToDebugState(PROCESSOR_STATE *state)
{
// Step 1. Read the DSCR to determine the cause of debug entry.
state->dscr := ReadDebugRegister(34);
// Step 2. Issue a DataSynchronizationBarrier instruction if required;
// this is not required by Cortex-R4 but is required for ARMv7
// debug.
if ((state->dscr & (1<<19)) == 0)
{
ExecuteARMInstruction(0xEE070F9A)
// Step 3. Poll the DSCR for DSCR[19] to be set.
repeat
{