ARM Cortex R4F - Manual (Page 42)

Introduction
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-21
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1.10 Product documentation, design flow, and architecture
This section describes the content of the product documents, how they relate to the design flow,
and the relevant architectural standards and protocols.
Note
See Further reading on page xx for more information about the documentation described in this
section.
1.10.1 Documentation
The following books describe the processor:
Technical Reference Manual
The Technical Reference Manual (TRM) describes the processor functionality
and the effects of functional options on the behavior of the processor. It is required
at all stages of the design flow. Some behavior described in the TRM might not
be relevant, because of the way the processor has been implemented and
integrated. If you are programming the processor, contact the implementer to
determine the build configuration of the implementation, and the integrator to
determine the pin configuration of the SoC that you are using.
Configuration and Sign-Off Guide
The Configuration and Sign-Off Guide (CSG) describes:
•
the available build configuration options and related issues in selecting
them
• how to configure the Register Transfer Level (RTL) with the build
configuration options
• the processes to sign off the configured RTL and final macrocell.
The ARM product deliverables include reference scripts and information about
using them to implement your design. Reference methodology documentation
from your EDA tools vendor complements the CSG. The CSG is a confidential
book that is only available to licensees.
Integration Manual
The Integration Manual (IM) describes how to integrate the processor into a SoC
including describing the pins that the integrator must tie off to configure the
macrocell for the required integration. Some of the integration is affected by the
configuration options that were used to implement the processor. Contact the
implementer of the macrocell that you are using to determine the implemented
build configuration options. The IM is a confidential book that is only available
to licensees.
1.10.2 Design flow
The processor is delivered as synthesizable RTL. Before it can be used in a product, it must go
through the following process:
1. Implementation. The implementer configures and synthesizes the RTL to produce a hard
macrocell. This includes integrating the cache RAMs into the design.
2. Integration. The integrator integrates the hard macrocell into a SoC, connecting it to a
memory system and to appropriate peripherals for the intended function. This memory
system includes the Tightly Coupled Memories (TCMs).