ARM Cortex R4F - Manual (Page 229)

Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-33
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; Clean entire data cache. This routine will depend on the data cache size. It can be
omitted if it is known that the data cache has no dirty data (e.g. if the cache has not
been enabled yet).
MRC p15, 0, r1, c1, c0, 1 ; Read Auxiliary Control Register
; Change bits 5:3 as needed
MCR p15, 0, r1, c1, c0, 1 ; Write Auxiliary Control Register
MCR p15, 0, r0, c15, c5, 0 ; Invalidate entire data cache
MCR p15, 0, r0, c7, c5, 0 ; Invalidate entire instruction cache
MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register
ORR r0, r0, #0x1 << 2
; Enable data cache bit
ORR r0, r0, #0x1 << 12 ; Enable instruction cache bit
DSB
MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register
ISB