ARM Cortex R4F - Manual (Page 265)

Level Two Interface
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-32
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Other examples of accessing cache RAMs
Normally ARADDRS[18:15] is a one-hot field, and only accesses one RAM at a time.
However, if you want to access two tag RAMs, such as banks 0 and 2 or banks 1 and 3 at the
same time, use:
•
ARADDRS[18:15] = 4'b0101 to access banks 0 and 2
• ARADDRS[18:15] = 4'b1010 to access banks 1 and 3.
This enables data to be read from two tag RAMs simultaneously, and the same data to be written
to two tag RAMs simultaneously. To write different data to each tag RAM, you must ensure only
one tag RAM is accessed at a time.
You can access any combination of dirty RAM banks simultaneously. For example, to access all
dirty RAM banks use:
ARADDRS[18:15] = 4'b1111.
If you break these rules, for example if you access tag RAM banks 0 and 1, no SLVERR
response is generated, and any attempt to read or write banks in other combinations or multiple
banks of other RAMs is Unpredictable.
Note
If you attempt to read or write cache RAMs outside the physical cache size implemented, the
MSBs for that read or write access are ignored. For example, accessing
0x10000000 or 0x00000000
addresses in the cache RAM accesses the same physical location
0x0
. This means that such
accesses are aliased and no errors are generated.
[14:11] ECC, way 1
[10:9] Outer attributes, way 1
[8] Dirty value, way 1
[7] Not used, read-as-zero
[6:3] ECC, way 0
[2:1] Outer attributes, way 0
[0] Dirty value, way 0
Table 9-43 Dirty register format, with ECC (continued)
Data bit Description