ARM Cortex R4F - Manual (Page 159)

System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-75
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To access the Build Options 2 Register, write CP15 with:
MRC p15, 0, <Rd>, c15, c2, 1 ; read Build Options 2 Register
[6:5] DCACHE_ES Indicates whether an error scheme is implemented for the data cache:
00 = no error scheme
01 = 8-bit parity error detection
10 = 32-bit error detection and correction.
If the processor does not contain a d-cache, these bits are set to 00.
[4] NO_HARD_ERROR_CACH
E Indicates whether the processor contains cache for corrected TCM errors:
0 = processor contains TCM error cache
1 = processor does not contain TCM error cache.
[3] AXIBUSPARITY Indicates whether the processor contains AXI bus parity logic.
0 = processor does not contain AXI bus parity logic
1 = processor contains AXI bus parity logic.
[2:0] Reserved Undefined.
a. The value of this bit is UNPREDICTABLE in revision r1p0 of the processor.
Table 4-55 Build Options 2 Register (continued)
Bits Field Function