ARM Cortex R4F - Manual (Page 66)

Programmer’s Model
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LIL behavior enables accesses to Normal memory, including multiword accesses and external
accesses, to be abandoned part-way through execution so that the processor can react to a
pending interrupt faster than would otherwise be the case. When an instruction is abandoned in
this way, the processor behaves as if the instruction was not executed at all. If, after handling the
interrupt, the interrupt handler returns to the program in the normal way using instruction
SUBS
pc, r14, #4
, the abandoned instruction is re-executed. This means that some of the memory
accesses generated by the instruction are performed twice.
Memory that is marked as Strongly Ordered or Device type is typically sensitive to the number
of reads or writes performed. Because of this, instructions that access Strongly Ordered or
Device memory are never abandoned when they have started accessing memory. These
instructions always complete either all or none of their memory accesses. Therefore, to
minimize the interrupt latency, you must avoid the use of multiword load/store instructions to
memory locations that are marked as Strongly Ordered or Device.
Interrupt controller
The processor includes a VIC port for connection of a Vectored Interrupt Controller (VIC). An
interrupt controller is a peripheral that handles multiple interrupt sources. Features usually
found in an interrupt controller are:
• multiple interrupt request inputs, one for each interrupt source, and one or more
amalgamated interrupt request outputs to the processor
• the ability to mask out particular interrupt requests
• prioritization of interrupt sources for interrupt nesting.
In a system with an interrupt controller with these features, software is still required to:
• determine from the interrupt controller which interrupt source is requesting service
• determine where the service routine for that interrupt source is loaded
• mask or clear that interrupt source, before re-enabling processor interrupts to allow
another interrupt to be taken.
A VIC does all these in hardware to reduce the interrupt latency. It supplies the starting address
of the service routine corresponding to the highest priority asserted interrupt source directly to
the processor. When the processor has accepted this address, it masks the interrupt so that the
processor can re-enable interrupts without clearing the source. The PL192 VIC is an Advanced
Microcontroller Bus Architecture (AMBA) compliant, System-on-Chip (SoC) peripheral that is
developed, tested, and licensed by ARM for use in Cortex-R4 designs.
You can use the VIC port to connect a PL192 VIC to the processor. See the ARM PrimeCell
Vectored Interrupt Controller (PL192) Technical Reference Manual for more information about
the PL192 VIC. You can enable the VIC port by setting the VE bit in the System Control
Register. When the VIC port is enabled and an IRQ occurs, the processor performs an handshake
over the VIC interface to obtain the address of the handling routine for the IRQ.
See the Cortex-R4 and Cortex-R4F Integration Manual for more information about the VIC
port, its signals, and their timings.
Interrupt entry flowchart
Figure 2-5 on page 2-21 is a flowchart for processor interrupt recognition. It shows all the
necessary decisions and actions for complete interrupt entry.