ARM Cortex R4F - Manual (Page 57)

Programmer’s Model
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-11
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• MRRC2
• PLD
•
RFE
•
SETEND
•
SRS
• STC2 .
In Thumb state, the processor can only execute the Branch instruction conditionally. Other
instructions can be made conditional by placing them in the If-Then (IT) block. For more
information about conditional execution in Thumb state, see the ARM Architecture Reference
Manual.
2.7.2 The Q bit
Certain multiply and fractional arithmetic instructions can set the Sticky Overflow, Q, flag:
•
QADD
• QDADD
•
QSUB
•
QDSUB
•
SMLAD
• SMLAxy
• SMLAWy
• SMLSD
•
SMUAD
•
SSAT
•
SSAT16
• USAT
• USAT16 .
The Q flag is sticky in that, when an instruction sets it, this bit remains set until an MSR instruction
writing to the CPSR explicitly clears it. Instructions cannot execute conditionally on the status
of the Q flag.
To determine the status of the Q flag you must read the PSR into a register and extract the Q flag
from this. For information of how the Q flag is set and cleared, see individual instruction
definitions in the ARM Architecture Reference Manual.
2.7.3 The IT bits
IT[7:5] encodes the base condition code for the current IT block, if any. It contains b000 when
no IT block is active.
IT[4:0] encodes the number of instructions that are to be conditionally executed, and whether
the condition for each is the base condition code or the inverse of the base condition code. It
contains b00000 when no IT block is active.
When an IT instruction is executed, these bits are set according to the condition in the
instruction, and the Then and Else (T and E) parameters in the instruction. During execution of
an IT block, IT[4:0] is shifted to:
• reduce the number of instructions to be conditionally executed by one
• move the next bit into position to form the least significant bit of the condition code.