ARM Cortex R4F - Manual (Page 316)

Debug
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-47
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11.8.7 Coprocessor instructions
CP14 and CP15 instructions can always be executed in debug state regardless of processor
mode.
11.8.8 Effect of debug state on non-invasive debug
The processor non-invasive debug features are the ETM and Performance Monitoring Unit
(PMU). All of these non-invasive debug features are disabled when the processor is in debug
state. For more information, see Chapter 4 System Control Coprocessor and ETM interface on
page 1-11.
When the processor is in debug state:
•
the ETM ignores all instructions and data transfers
• PMU events are not counted
• events are not visible to the ETM
• the PMU Cycle Count Register (CCNT) is stopped.
11.8.9 Effects of debug events on processor registers
On entry to debug state, the processor does not update any general-purpose or program status
register. This includes the SPSR_abt and R14_abt registers. In addition, the processor does not
update any coprocessor registers, including the CP15 IFSR, DFSR, DFAR, or IFAR registers,
except for CP14 DSCR[5:2] method-of-entry bits. These bits indicate the type of debug event
that caused the entry into debug state.
Note
On entry to debug state, the processor updates the WFAR register with the address of the
instruction accessing the watchpointed address plus:
•
+ 8 in ARM state
• + 4 in Thumb state.
11.8.10 Exceptions in debug state
While in debug state, exceptions are handled as follows:
Reset This exception is taken as in a normal processor state. This means the processor
leaves debug state because of the system reset.
Prefetch Abort
This exception cannot occur because the processor does not fetch any instructions
while in debug state.
Debug The processor ignores debug events, including BKPT instructions.
SVC The processor ignores SVC exceptions.
Undefined
When an Undefined exception occurs in debug state, the behavior of the
processor is as follows:
•
PC, CPSR, SPSR_und, and R14_und are unchanged
• the processor remains in debug state
• DSCR[8], sticky Undefined bit, is set.