ARM Cortex R4F - Manual (Page 218)

Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-22
ID013010 Non-Confidential, Unrestricted Access
Handling cache ECC errors
Table 8-3 shows the behavior of the processor on a cache ECC error, depending on bits [5:3] of
the Auxiliary Control Register, see Auxiliary Control Registers on page 4-38.
See Disabling or enabling error checking on page 8-32 for information on how to safely change
these bits.
When ECC checking is enabled, hardware recovery is always enabled. When an ECC error is
detected, the processor tries to evict the cache line containing the error. If the line is clean, it is
invalidated, and the correct data is reloaded from the L2 memory system. If the line is dirty, the
eviction writes the dirty data out to the L2 memory system, and in the process it corrects any
1-bit errors. The corrected data is then reloaded from the L2 memory system.
If a 2-bit error is detected in a dirty line, the error is not correctable. If the 2-bit error is in the
tag or dirty RAM, no data is written to the L2 memory system. If the 2-bit error is in the data
RAM, the cache line is written to the L2 memory system, but the AXI master port WSTRBM
signal is LOW for the data that contains the error. If an uncorrectable error is detected, an abort
is always generated because data might have been lost. It is expected that such a situation can
be fatal to the software process running.
If one of the force write-though settings is enabled, memory marked as write-back write-allocate
behaves as write-though. This ensures that cache lines can never be dirty, therefore the error can
always be recovered from by invalidating the cache line that contains the ECC error.
All detectable errors in the instruction cache can always be recovered from because the
instruction cache can never contain dirty data.
ECC aborts
If aborts on ECC errors are enabled, software is notified of the error by a data abort or prefetch
abort. The error is still automatically corrected by the hardware even if an abort is generated.
If abort generation is not enabled, the hardware recovery is invisible to software. If required,
software can use events and the Correctable Fault Location Register to monitor the errors that
are detected and corrected. See Error detection events on page 8-36 and Correctable Fault
Location Register on page 4-70.
Table 8-3 Cache ECC error behavior
Value Behavior
b000 Abort on all ECC errors, enable hardware recovery
b001
b010 Abort on all ECC errors, force write-through, enable hardware recovery
b011 Reserved
b100 Disable ECC checking
b101 Enable hardware recovery, do not generate aborts on ECC errors
b110 Force write-through, enable hardware recovery, do not generate aborts on ECC errors
b111 Reserved