ARM Cortex R4F - Manual (Page 263)

Level Two Interface
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-30
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Note
For tag RAM writes, only bits [23:0] of the data bus are used. If two tag RAMs are written at
the same time, they are both written with the same data. To write only one tag RAM using the
AXI Slave, select only one RAM with bits [18:15] of the address bus.
[31:30] Not used, read-as-zero
[29:23] ECC, way 0/1
[22] Valid, way 0/1
[21:0] Tag value, way 0/1
Table 9-39 Tag register format for writes, no parity or ECC
Data bit Description
[63:23] Not used, read-as-zero
[22] Valid, all ways
[21:0] Tag value, all ways
Table 9-40 Tag register format for writes, with parity
Data bit Description
[63:24] Not used, read-as-zero
[23] Parity. all ways
[22] Valid, all ways
[21:0] Tag value, all ways
Table 9-41 Tag register format for writes, with ECC
Data bit Description
[63:30] Not used, read-as-zero
[29:23] ECC, all ways
[22] Valid, all ways
[21:0] Tag value, all ways
Table 9-38 Tag register format for reads, with ECC (continued)
Data bit Description