ARM Cortex R4F - Manual (Page 149)

System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-65
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The nVAL Debug Request Enable Set Register is:
• A read/write register.
• Always accessible in Privileged mode. The USEREN Register determines access, see c9,
User Enable Register on page 6-15.
Figure 4-47 shows the bit arrangement for the nVAL Debug Request Enable Set Register.
Figure 4-47 nVAL Debug Request Enable Set Register format
Table 4-45 shows how the bit values correspond with the nVAL Debug Request Enable Set
Register.
To access the nVAL Debug Request Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 3 ; Read nVAL Debug Request Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 3 ; Write nVAL Debug Request Enable Set Register
On reads, this register returns the current setting. On writes, debug requests can be enabled. If
a debug request has been enabled, it is disabled by writing to the nVAL Debug Request Enable
Clear Register. See c15, nVAL Debug Request Enable Clear Register on page 4-68.
If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding
counter overflows, then a debug reset request is indicated by VALEDBGRQ being asserted
HIGH. This signal can be passed to an external debugger.
c15, nVAL IRQ Enable Clear Register
The nVAL IRQ Enable Clear Register disables overflow IRQ requests from any of the PMC
Registers, PMC0-PMC2, and CCNT, for which they have been enabled.
The nVAL IRQ Enable Clear Register is:
• A read/write register.
• Always accessible in Privileged mode. The USEREN Register determines access, see c9,
User Enable Register on page 6-15.
Figure 4-48 on page 4-66 shows the bit arrangement for the nVAL IRQ Enable Clear Register.
C
31 3 2 1 0
Reserved
P2
P1
P0
Performance monitor counter
overflow debug request enables
Cycle count overflow debug request enable
Table 4-45 nVAL Debug Request Enable Set Register bit functions
Bits Field Function
[31] C CCNT overflow debug request
[30:3] Reserved UNP or SBZP
[2] P2 PMC2 overflow debug request
[1] P1 PMC1 overflow debug request
[0] P0 PMC0 overflow debug request