ARM Cortex R4F - Manual (Page 431)

Processor Signal Descriptions
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-18
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DBGROMADDRV Input Tie-off Debug ROM physical address valid
DBGSELFADDR[31:12] Input Tie-off Debug self-address offset
DBGSELFADDRV Input Tie-off Debug self-address offset valid
a. Not available in r0px revisions of the processor.
Table A-13 Debug miscellaneous signals (continued)
Name Direction Clocking Description