Table 4-36, Functional bits of c7 for set and way -56, Table 4-37 – ARM Cortex R4F User Manual

Page 140: Widths of the set field for l1 cache sizes -56, Figure 4-39, C7 format for set and way -56, Figure 4-40, Cache operations address format -56

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Table 4-36, Functional bits of c7 for set and way -56, Table 4-37 | Widths of the set field for l1 cache sizes -56, Figure 4-39, C7 format for set and way -56, Figure 4-40, Cache operations address format -56 | ARM Cortex R4F User Manual | Page 140 / 456 Table 4-36, Functional bits of c7 for set and way -56, Table 4-37 | Widths of the set field for l1 cache sizes -56, Figure 4-39, C7 format for set and way -56, Figure 4-40, Cache operations address format -56 | ARM Cortex R4F User Manual | Page 140 / 456
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Cortex r1p3, Cortex R4

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