3 linefills, 4 cache line write-back (eviction), 5 non-cacheable reads – ARM Cortex R4F User Manual

Page 246: Table 9-12, Linefill behavior on the axi interface -13, Table 9-13, Cache line write-back -13, Table 9-14, Ldrh from non-cacheable normal memory -13

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3 linefills, 4 cache line write-back (eviction), 5 non-cacheable reads | Table 9-12, Linefill behavior on the axi interface -13, Table 9-13, Cache line write-back -13, Table 9-14, Ldrh from non-cacheable normal memory -13 | ARM Cortex R4F User Manual | Page 246 / 456 3 linefills, 4 cache line write-back (eviction), 5 non-cacheable reads | Table 9-12, Linefill behavior on the axi interface -13, Table 9-13, Cache line write-back -13, Table 9-14, Ldrh from non-cacheable normal memory -13 | ARM Cortex R4F User Manual | Page 246 / 456
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This manual is related to the following products:

Cortex r1p3, Cortex R4

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