ARM Cortex R4F - Manual (Page 138)

System Control Coprocessor
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4.2.20 Cache operations
The purpose of c7 is to manage the associated caches. The maintenance operations are formed
into two management groups:
•
Set and Way:
—
clean
— invalidate
— clean and invalidate.
• Address, usually labelled MVA for Modified Virtual Address, but on this processor all
addresses are identical:
—
clean
— invalidate
— clean and invalidate.
In addition, the maintenance operations use these definitions:
Point of Coherency (PoC)
A point where all instruction, data, or translation-table walks are transparent to
any processor in the system.
Point of Unification (PoU)
A point where instruction and data become unified and self-modifying code can
function.
Figure 4-38 on page 4-55 shows the arrangement of the functions in this group that operate with
the
MCR and MRC instructions.
Note
The following operations, as Figure 4-38 on page 4-55 shows, are implemented as No
Operation,
NOP
, on the processor:
• Wait For Interrupt, CRm= c0, Opcode_2 = 4
• Invalidate Entire Branch Predictor Array, CRm= c5, Opcode_2 = 6
• Invalidate Branch Predictor Array Line using MVA, CRm= c5, Opcode_2 = 7
The Wait For Interrupt ( WFI ) instruction provides the Wait For Interrupt function. For more
information see the ARM Architecture Reference Manual.