ARM Cortex R4F - Manual (Page 17)

Preface
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xvii
ID013010 Non-Confidential, Unrestricted Access
About this book
This is the Technical Reference Manual (TRM) for the Cortex-R4 and Cortex-R4F processors.
In this book the generic term processor means both the Cortex-R4 and Cortex-R4F processors.
Any differences between the two processors are described where necessary.
Note
The Cortex-R4F processor is a Cortex-R4 processor that includes the optional Floating Point
Unit (FPU) extension, see Product revision information on page 1-24 for more information.
In this book, references to the Cortex-R4 processor also apply to the Cortex-R4F processor,
unless the context makes it clear that this is not the case.
Product revision status
The rnpn identifier indicates the revision status of the product described in this book, where:
rn
Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
This book is written for system designers, system integrators, and programmers who are
designing or programming a System-on-Chip (SoC) that uses the processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the processor and descriptions of the major
functional blocks.
Chapter 2 Programmer’s Model
Read this for a description of the processor registers and programming
information.
Chapter 3 Processor Initialization, Resets, and Clocking
Read this for a description of clocking and resetting the processor, and the steps
that the software must take to initialize the processor after reset.
Chapter 4 System Control Coprocessor
Read this for a description of the system control coprocessor registers and
programming information.
Chapter 5 Prefetch Unit
Read this for a description of the functions of the Prefetch Unit (PFU), including
dynamic branch prediction and the return stack.
Chapter 6 Events and Performance Monitor
Read this for a description of the Performance Monitoring Unit (PMU) and the
event bus.
Chapter 7 Memory Protection Unit