ARM Cortex R4F - Manual (Page 196)

Memory Protection Unit
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-13
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7.6 MPU software-accessible registers
Figure 4-2 on page 4-5 shows the CP15 registers that control the MPU.
When the MPU is not present, the c6, MPU memory region programming registers on page 4-49
read as zero and ignore writes in Privileged mode. No Undefined instruction exceptions are
taken.