Altera Cyclone II DSP Development Board User Manual
Page 101
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Altera Corporation
Reference Manual
C–15
August 2006
Cyclone II DSP Development Board
GND
AE1
M12
GND
GND
AE26
M13
GND
GND
AF12
M14
GND
GND
AF15
M15
GND
GND
AF2
M16
1.2V
GND
AF25
M17
1.2V
GND
AF8
M18
3.3V
GND
B1
M19
EVM_D2
GND
B26
M2
PROTO_IO24
GND
C14
M20
EVM_D6
GND
C18
M21
EVM_CNTL0
GND
D24
M22
EVM_INT0
GND
D4
M23
EVM_BEN1
GND
E11
M24
EVM_BEN3
GND
E16
M25
EVM_INT1
GND
E19
M26
GND
GND
E7
M3
PROTO_IO23
GND
G17
M4
DAC_B_D0
GND
G20
M5
DAC_B_D1
GND
G7
M6
JTAG_TCK
GND
H12
M7
JTAG_CONN_TDI
GND
H13
M8
JTAG_CONN_TDO
GND
H14
M9
3.3V
GND
H22
N1
GND
GND
H5
N10
1.2V
GND
H8
N11
GND
GND
J10
N12
GND
GND
J11
N13
GND
GND
J13
N14
GND
GND
J14
N15
GND
GND
J16
N16
GND
GND
J17
N17
1.2V
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 15 of 22)
Note (1)
Alphabetical by Signal Name
Alphabetical by Pin Number
Schematic Signal Name
Pin Number
Pin Number
Schematic Signal Name
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