Altera Cyclone II DSP Development Board User Manual
Page 107
Altera Corporation
Reference Manual
C–21
August 2006
Cyclone II DSP Development Board
VGA_B5
W1
W21
DIG_MSB_G
VGA_B6
U4
W22
GND
VGA_B7
U2
W23
EVM_ARDY
VGA_BLANKN
U6
W24
EVM_D13
VGA_CLK
T4
W25
DAC_B_D10
VGA_G0
R3
W26
DAC_B_D11
VGA_G1
W6
W3
VGA_B1
VGA_G2
R7
W4
AUDIO_LRCIN
VGA_G3
U5
W5
GND
VGA_G4
R6
W6
VGA_G1
VGA_G5
AA4
W7
GND
VGA_G6
T6
W8
GND
VGA_G7
V4
W9
1.8V
VGA_HSYNC
H21
Y1
ADC_SDATA
VGA_R0
Y22
Y10
DIMM_A_R3
VGA_R1
T22
Y11
DIMM_DQ28
VGA_R2
AD25
Y12
DIMM_A_R12
VGA_R3
T20
Y13
DIMM_DQ12
VGA_R4
AC23
Y14
DIMM_DQ13
VGA_R5
U21
Y15
DIMM_DQ8
VGA_R6
P4
Y16
DIMM_DQ4
VGA_R7
Y25
Y17
GND
VGA_SYNCN
AE2
Y18
DIMM_BA_R0
VGA_VSYNC
F21
Y19
GND_PLL
VREF
AA14
Y2
VREF
AC10
Y20
1.2V
VREF
AC12
Y21
DIG_MSB_A
VREF
AC16
Y22
VGA_R0
VREF
AC7
Y23
EPCS_USER_CSN
VREF
D11
Y24
DAC_B_D8
VREF
D16
Y25
VGA_R7
VREF
D5
Y26
EVM_D11
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 21 of 22)
Note (1)
Alphabetical by Signal Name
Alphabetical by Pin Number
Schematic Signal Name
Pin Number
Pin Number
Schematic Signal Name