Altera Cyclone II DSP Development Board User Manual
Page 106
C–20
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Introduction
PROTO_IO9
F4
V16
1.2V
SRAM_CLK
R25
V17
GND
USER_DIPSW0
AC13
V18
1.2V
USER_DIPSW1
A19
V19
3.3V
USER_DIPSW2
C21
V2
PROTO_CARDSELN
USER_DIPSW3
C23
V20
DAC_B_D3
USER_DIPSW4
AF4
V21
DAC_B_D4
USER_DIPSW5
AC20
V22
EVM_D0
USER_DIPSW6
AE18
V23
EVM_BWEN
USER_DIPSW7
AE19
V24
DAC_B_D9
USER_LED0
E5
V25
DAC_B_D12
USER_LED1
B3
V26
EVM_D17
USER_LED2
F20
V3
DIG_MSB_DP
USER_LED3
E22
V4
VGA_G7
USER_LED4
AC3
V5
DAC_A_D8
USER_LED5
AB4
V6
DAC_A_D9
USER_LED6
AA6
V7
DIG_LSB_E
USER_LED7
AA7
V8
3.3V
USER_PB0
AC18
V9
1.2V
USER_PB1
AE16
W1
VGA_B5
USER_PB2
AE22
W10
1.2V
USER_PB3
AE14
W11
1.2V
USER_RESETN
A14
W12
GND
VCCA_PLL1
AA8
W13
GND
VCCA_PLL2
G19
W14
GND
VCCA_PLL3
G8
W15
1.2V
VCCA_PLL4
AA19
W16
1.2V
VGA_B0
AC1
W17
1.2V
VGA_B1
W3
W18
1.8V
VGA_B2
B2
W19
GND
VGA_B3
W2
W2
VGA_B3
VGA_B4
H2
W20
GND
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 20 of 22)
Note (1)
Alphabetical by Signal Name
Alphabetical by Pin Number
Schematic Signal Name
Pin Number
Pin Number
Schematic Signal Name