Intel 386 - Manual (Page 11)

Intel386™ EX MICROPROCESSOR USER’S MANUAL
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13.2.3 Receiver ................................................................................................................13-12
13.3 REGISTER DEFINITIONS......................................................................................... 13-16
13.3.1 Pin Configuration Register (PINCFG) ...................................................................13-17
13.3.2 SIO and SSIO Configuration Register (SIOCFG) .................................................13-18
13.3.3 Prescale Clock Register (CLKPRS) ......................................................................13-19
13.3.4 SSIO Baud-rate Control Register (SSIOBAUD) ....................................................13-20
13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR) ..............................................13-21
13.3.6 SSIO Control 1 Register (SSIOCON1) ..................................................................13-21
13.3.7 SSIO Control 2 Register (SSIOCON2) ..................................................................13-23
13.3.8 SSIO Transmit Holding Buffer (SSIOTBUF) .........................................................13-24
13.3.9 SSIO Receive Holding Buffer (SSIORBUF) ..........................................................13-25
13.4 DESIGN CONSIDERATIONS.................................................................................... 13-25
13.5 PROGRAMMING CONSIDERATIONS...................................................................... 13-26
13.5.1 SSIO Example Code .............................................................................................13-26
CHAPTER 14
CHIP-SELECT UNIT
14.1 OVERVIEW ................................................................................................................. 14-1
14.2 CSU UPON RESET ..................................................................................................... 14-2
14.3 CSU OPERATION ....................................................................................................... 14-2
14.3.1 Defining a Channel’s Address Block .......................................................................14-2
14.3.2 System Management Mode Support ....................................................................14-10
14.3.3 Bus Cycle Length Control .....................................................................................14-11
14.3.4 Bus Size Control ...................................................................................................14-11
14.3.5 Overlapping Regions ............................................................................................14-11
14.4 REGISTER DEFINITIONS......................................................................................... 14-13
14.4.1 Pin Configuration Register (PINCFG) ...................................................................14-15
14.4.2 Port 2 Configuration Register (P2CFG) ................................................................14-16
14.4.3 Chip-select Address Registers ..............................................................................14-17
14.4.4 Chip-select Mask Registers ..................................................................................14-19
14.5 DESIGN CONSIDERATIONS.................................................................................... 14-21
14.6 PROGRAMMING CONSIDERATIONS...................................................................... 14-22
14.6.1 Chip-Select Unit Code Example ............................................................................14-22
CHAPTER 15
REFRESH CONTROL UNIT
15.1 DYNAMIC MEMORY CONTROL................................................................................. 15-1
15.1.1 Refresh Methods .....................................................................................................15-1
15.2 REFRESH CONTROL UNIT OVERVIEW ................................................................... 15-2
15.2.1 RCU Signals ...........................................................................................................15-4
15.2.2 Refresh Intervals .....................................................................................................15-4