Intel 386 - Manual (Page 618)

D-53
SYSTEM REGISTER QUICK REFERENCE
D.51 REMAPCFG
Address Configuration Register
REMAPCFG Expanded Addr:
PC/AT Address:
Reset State: 0022H
0022H
0000H
15 8
ESE — — — — — — —
7 0
— S1R S0R ISR IMR DR — TR
Bit
Number
Bit
Mnemonic
Function
15 ESE 0 = Disables expanded I/O space
1 = Enables expanded I/O space
14–7 — Reserved.
6 S1R 0 = Makes serial channel 1 (COM2) accessible in both DOS I/O space
and expanded I/O space
1 = Remaps serial channel 1 (COM2) address into expanded I/O space
5 S0R 0 = Makes serial channel 0 (COM1) accessible in both DOS I/O space
and expanded I/O space
1 = Remaps serial channel 0 (COM1) address into expanded I/O space
4 ISR 0 = Makes the slave 82C59A interrupt controller accessible in both DOS
I/O space and expanded I/O space
1 = Remaps slave 82C59A interrupt controller address into expanded
I/O space
3 IMR 0 = Makes the master 82C59A interrupt controller accessible in both
DOS I/O space and expanded I/O space
1 = Remaps master 82C59A interrupt controller address into expanded
I/O space
2 DR 0 = Makes the DMA address accessible in both DOS I/O space and
expanded I/O space
1 = Remaps DMA address into expanded I/O space
1 — Reserved.
0 TR 0 = Makes the timer control unit accessible in both DOS I/O space and
expanded I/O space
1 = Remaps timer control unit address into expanded I/O space