Intel 386 - Manual (Page 235)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
9-36
_IRQ_SlaveBase_ = SlaveBase & 0xf8;
_SetEXRegByte(ICW1S, 0x11 | SlaveMode); // Set slave triggering
_SetEXRegByte(ICW2S, _IRQ_SlaveBase_); // Set slave base interrupt
// type, least 3-bit must be 0
_SetEXRegByte(ICW3S, 0x2); // Set slave ID
_SetEXRegByte(ICW4S, 0x1); // Set bit 0 to guarantee
// operation
cfg_pins = _GetEXRegByte(INTCFG);
cfg_pins |= SlavePins;
_SetEXRegByte(INTCFG, SlavePins); // Set Slave external interrupt
// pins
return E_OK;
}/* InitICUSlave */
/*****************************************************************************
Disable8259Interrupt:
Description:
Disables 8259a interrupts for the master and the slave.
Parameters:
MstrMask Mask value for master ICU
SlaveMask Mask value for slave ICU
Each bit location that is set disables the corresponding
interrupt (by setting the bit in the interrupt control register).
For example, to disable master IR3 and IR5 set MstrMask = 0x28
(bits 3 and 5 are set).
Returns:
None
Assumptions:
REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
Syntax:
/* ICU IRQ Mask Values*/
#define IR0 0x1
#define IR1 0x2
#define IR2 0x4
#define IR3 0x8
#define IR4 0x10
#define IR5 0x20
#define IR6 0x40