Intel 386 - Manual (Page 514)

18-1
CHAPTER 18
JTAG TEST-LOGIC UNIT
The JTAG test-logic unit enables you to test both the device logic and the interconnections be-
tween the device and the board (system) it is plugged into. The term JTAG refers to the Joint Test
Action Group, the IEEE technical subcommittee that developed the testability standard published
as Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
†
and
its supplement, Standard 1149.1a-1993. The Intel386
TM
EX Embedded Processor JTAG test-log-
ic unit is fully compliant with this standard.
You can use the JTAG unit for other purposes. For example you can perform in-system program-
ming of flash memory; refer to AP-720, Programming Flash Memory through the Intel386™ EX
Embedded Processor JTAG Port (order number 272753).
This chapter is organized as follows:
• Overview (see below)
• Test-Logic Unit Operation (page 18-3)
• Testing (page 18-10)
• Timing Information (page 18-12)
• Design Considerations (page 18-14)
18.1 OVERVIEW
As the title of the IEEE standard suggests, two major components of the test-logic unit are the test
access port and the boundary-scan register. The term test access port (TAP) refers to the dedicat-
ed input and output pins through which a tester communicates with the test-logic unit. The term
boundary-scan refers to the ability to scan (observe) the signals at the boundary (the pins) of a
device. A boundary-scan cell resides at each pin. These cells are connected serially to form the
boundary-scan register, which allows you to control or observe every device pin except the clock
pin, the power and ground pins, and the test access port pins.
The test-logic unit allows a tester to perform these tasks:
• Identify a component on a board (manufacturer, part number, and version)
• Bypass one or more components on a board while testing others
• Preload a pin state for a test or read the current pin state
• Perform static (slow-speed) testing of this device
• Test off-chip circuitry and board-level interconnections
† Some of the figures and tables in this chapter were reproduced from Standard 1149.1-1990, IEEE Standard Test
Access Port and Boundary-Scan Architecture, Copyright 1993 by the Institute of Electrical and Electronics Engineers,
Inc., with the permission of the IEEE.