Intel 386 - Manual (Page 145)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
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The BS8 cycle generates additional bus cycles for read and write cycles only. For interrupt and
halt/shutdown cycles, the accesses are byte wide and the BS8# signal is ignored. For a refresh
cycle, the byte enables are both disabled and the BS8# signal is ignored.
NOTE
If a BS8 cycle requires an additional bus cycle, the processor retains the
current address for the second cycle. Address pipelining cannot be used with
BS8 cycles because address pipelining requires that the next address be
generated on the bus before the end of the current bus cycle. NA# must be kept
deasserted during the T2 states of BS8 memory cycles. NA# is ignored in all
I/O cycles.
NOTE
BS8# must be inactive at the falling edge of PH2 of the T1 state of a non-BS8
cycle; for example, if the current cycle is a BS8 cycle (BS8# asserted) and the
next cycle is not a BS8 cycle, BS8# must be deasserted before the end of the
T1 state of the next cycle, i.e. the non-BS8 cycle.