Intel 386 - Manual (Page 400)

13-1
CHAPTER 13
SYNCHRONOUS SERIAL I/O UNIT
The synchronous serial I/O (SSIO) unit provides 16-bit bidirectional serial communications. The
transmit and receive channels can operate independently (that is, with different clocks) to provide
full-duplex communications. Either channel can originate the clocking signal or receive an exter-
nally generated clocking signal.
This chapter is organized as follows:
• Overview (see below)
• SSIO Operation (page 13-5)
• Register Definitions (page 13-16)
• Design Considerations (page 13-25)
• Programming Considerations (page 13-26)
13.1 OVERVIEW
The SSIO unit contains a baud-rate generator, transmitter, and receiver. The baud-rate generator
has two possible internal clock sources (PSCLK or SERCLK). The transmitter and receiver are
double buffered. They contain 16-bit holding buffers and 16-bit shift registers. Data to be trans-
mitted is written to the transmit holding buffer. The buffer’s contents are transferred to the trans-
mit shift register and shifted out via the serial data transmit pin (SSIOTX). Data received is
shifted in via the serial data receive pin (SSIORX). Once 16 bits have been received, the contents
of the receive shift register are transferred to the receive buffer.
Both the transmitter and receiver can operate in either master or slave mode. In master mode, the
internal baud-rate generator controls the serial communications by clocking the internal transmit-
ter or receiver. If the transmitter or receiver is enabled in master mode, the baud-rate generator’s
signal appears on the transmit or receive clock pin, and is available for clocking an external slave
transmitter or receiver. In slave mode, an external master device controls the serial communica-
tions. An input on the external transmit or receive clock pin clocks the transmitter or receiver. The
transmitter and receiver need not operate in the same mode. This allows the transmitter and re-
ceiver to operate at different frequencies (an internal and an external clock source or two different
external clock sources can be used). Figures 13-1 through 13-4 illustrate the various transmit-
ter/receiver master/slave combinations.