Intel 386 - Manual (Page 205)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
9-6
Interrupt processing begins with the assertion of an IR signal. During the ICU initialization pro-
cess (described in “Register Definitions” on page 9-15), you can program the ICU to be either
edge-triggered or level-triggered. See “Interrupt Detection” on page 9-29 for a description of the
difference between level and edge triggered signals.
9.2.2 Interrupt Priority
Each 82C59A contains eight interrupt request signals. An 82C59A can receive several concurrent
interrupt requests or can receive a request while the core is servicing another interrupt. When ei-
ther condition occurs, the 82C59A uses a programmable priority structure to determine the order
in which to process the interrupts. There are two parts to the priority structure:
• Assigning an interrupt level to each IR signal
• Determining their relative priorities
9.2.2.1 Assigning an Interrupt Level
By default, the interrupt structure for each 82C59A is configured so that IR0 has the highest level
and IR7 has the lowest level. Two methods (shown in Figure 9-2) are available for changing this
interrupt structure:
Specific Rotation This method assigns a specific IR signal as the lowest level. The
other IR signals are automatically rearranged in a circular manner.
For example, if you specify IR5 as the lowest level, IR6 becomes the
highest level, IR7 becomes the second-highest, and so on, with IR4
the second-lowest.
Automatic Rotation This method assigns an IR signal to the lowest level after the core
services its interrupt. As with specific rotation, the other signals are
automatically rearranged in a circular manner. For example, the IR4
signal is assigned the lowest level after the core services its interrupt,
IR5 becomes the highest level, IR6 becomes the second-highest, and
so on, with IR3 the second-lowest.