Intel 386 - Manual (Page 353)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
12-18
12.2.7.2 Block Data-transfer Mode
In block data-transfer mode, a channel request initiates a buffer transfer. The channel gains bus
control, then transfers the entire buffer of data. The DRQn signal only needs to be held active until
DACKn# is active.
NOTE
Block mode, unlike the single mode, only gives up control of the bus for
DRAM refresh cycles.
As with single mode, the channel’s buffer-transfer mode determines whether the channel be-
comes idle or is reprogrammed after the buffer transfer completes or is terminated.
The block data-transfer mode is compatible with the single and autoinitialize buffer-transfer
modes, but not with the chaining buffer-transfer mode. The chaining buffer-transfer mode
requires that the transfer information for the next buffer transfer be written to the channel before
the current buffer transfer completes. This is impossible with block data-transfer mode, because
the channel only relinquishes control of the bus for DRAM refresh cycles during the buffer
transfer. The following flowcharts show the transfer process flow for a channel programmed for
the block data-transfer mode with the single (Figure 12-11) and autoinitialize (Figure 12-12)
buffer-transfer modes.