Intel 386 - Manual (Page 664)

E-27
INSTRUCTION SET SUMMARY
Table E-7. Encoding of 16-bit Address Mode with “mod r/m” Byte
mod r/m Effective Address mod r/m Effective Address
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
DS:[BX + SI]
DS:[BX + DI]
SS:[BP + SI]
SS:[BP + DI]
DS:[SI]
DS:[DI]
DS:d16
DS:[BX]
DS:[BX + SI + d8]
DS:[BX + DI + d8]
SS:[BP + SI + d8]
SS:[BP + DI + d8]
DS:[SI + d8]
DS:[DI + d8]
SS:[BP + d8]
DS:[BX + d8]
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
DS:[BX + SI + d16]
DS:[BX + DI + d16]
SS:[BP + SI + d16]
SS:[BX + DI + d16]
DS:[SI + d16]
DS:[DI + d16]
SS:[BP + d16]
DS:[BX + d16]
register - see tables below
register - see tables below
register - see tables below
register - see tables below
register - see tables below
register - see tables below
register - see tables below
register - see tables below
Register Specified by r/m
During 16-bit Data Operations
mod r/m
Function of w Field
(when w = 0) (when w = 1)
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
AL
CL
DL
BL
AH
CH
DH
BH
AX
CX
DX
BX
SP
BP
SI
DI
Register Specified by r/m
During 32-bit Data Operations
mod r/m
Function of w Field
(when w = 0) (when w = 1)
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
AL
CL
DL
BL
AH
CH
DH
BH
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI