Intel 386 - Manual (Page 687)

INTEL386™ EX MICROPROCESSOR USER’S MANUAL
Index-8
SSIOTBUF, 13-16 , 13-24 , D-61
TBRn, 11-15, 11-23, D-61
TMRCFG, 5-13 , 10-4 , 10-21 , D-62
TMRCON, 10-4 , 10-25 , 10-28 , 10-30 , D-63
TMRn, 10-4, 10-26, 10-29, 10-32, D-64, D-65
UCSADH, 14-14 , 14-17 , D-8
UCSADL, 14-14 , 14-18 , D-9
UCSMSKH, 14-14 , 14-19 , D-10
UCSMSKL, 14-14 , 14-20 , D-11
WDTCLR, 17-7
WDTCNTH, 17-7 , 17-8 , D-67
WDTCNTL, 17-7 , 17-8 , D-67
WDTRLDH, 17-7 , 17-10 , D-68
WDTRLDL, 17-7 , 17-10 , D-68
WDTSTATUS, 17-7 , 17-9 , D-69
reload event, 17-4
Reserved bits, defined, 1-5
Reset
considerations, 8-11
CPU-only, B-4
Resume instruction (RSM), 7-15
RSM, See Resume instruction
S
Scratch pad registers
SCRn, 11-32, D-56
Segment Descriptor Cache, 3-5
Segmentation Unit, 3-4 , 3-5
SERCLK, 8-1 – 8-2 , 11-1 , 11-4 , 11-21 , 13-1 ,
13-5 , 13-18
Serial I/O unit, 11-1 – 11-45
block diagram, 11-2
configuring, 5-14
departure from PC/AT architecture, B-3
DMA service, 5-3 – 5-5
operation, 11-4 – 11-14
baud-rate generator, 11-4 – 11-5
data transmission process flow, 11-8
diagnostic mode, 11-12
interrupt sources, 11-13
modem control, 11-12
receiver, 11-9 – 11-10
transmitter, 11-6 – 11-8
overview, 11-1 – 11-3
programming
accessing multiplexed registers, 11-16
considerations, 11-32
DLHn register, 11-22
DLLn register, 11-22
IERn register, 11-27
IIRn register, 11-28
LCRn, 11-25, D-36
LCRn register,
11-25
LSRn, 11-26, D-37
LSRn register,
11-26
MCRn, 11-30, D-38
MCRn register,
11-29 – 11-30
modem control signals, 11-29 – 11-30
MSRn, 11-31, D-39
MSRn register,
11-31
P1CFG register, 11-18
P2CFG register, 11-19
P3CFG register, 11-20
PINCFG register, 11-17
RBRn, 11-24, D-52
RBRn register,
11-24
SCRn register, 11-32
SIOCFG, 5-17 , 11-21 , 13-18 , D-57
SIOCFG register, 11-21
TBRn, 11-23, D-61
TBRn register,
11-23
register addresses, 4-19 , 4-20 , D-5 , D-6
registers, 11-15 – 11-16
signals, 11-3
Set, defined, 1-5
Signal descriptions, A-1 – A-10
Signal names, notational conventions, 1-4
SIO, See Serial I/O unit
SMM, See System management mode
SMM, see System Management Mode, 7-3
SMRAM, 7-2
chip-select unit support for, 7-12
state dump area, 7-14
Specific EOI command, 9-14
SSIO, See Synchronous serial I/O unit
Synchronous serial I/O unit, 13-1 – 13-25
configuring, 5-18
design considerations, 13-25
DMA service, 5-3
master/slave mode arrangements, 13-2 – 13-3