Intel 386 - Manual (Page 208)

9-9
INTERRUPT CONTROL UNIT
9.2.4 Interrupt Process
Each IR signal has a mask, a pending, and an in-service bit associated with it.
• The mask bit disables the IR signal. The respective mask bits provide a way to individually
disable the IR signals. You can globally disable all interrupts to the core using the CLI
instruction. The mask bits reside in the OCW1.
• The pending bit indicates that the IR signal is requesting interrupt service. The pending bit
resides in the IRR (Interrupt Request Register, which is accessed through OCW3).
• The in-service bit indicates that the processor is in the process of servicing the interrupt.
The in-service bit resides in the ISR (Interrupt Service Register, which is accessed through
OCW3).
When the master 82C59A receives an interrupt request, it sets the corresponding pending bit and
sends the request to the core (assuming the request is enabled and has sufficient priority). The
core then initiates an acknowledge cycle: the master clears its pending bit, sets its in-service bit,
and puts the interrupt vector number on the bus.
When the slave 82C59A receives an interrupt request, it sets the corresponding pending bit and
sends the request to the master (assuming the request is enabled and has sufficient priority). When
the master receives the slave request, it sets its IR2 pending bit and sends the IR2 request to the
core (assuming the request is enabled and has sufficient priority). The core initiates an interrupt
acknowledge cycle: the master clears its IR2 pending bit and sets its IR2 in-service bit. The mas-
ter’s cascade bus activates the slave, which responds to the interrupt acknowledge cycle, clears
its pending bit, sets its in-service bit, and puts the interrupt vector number on the bus.
An 82C59A uses its in-service bits and programmed priority structure to determine whether an
interrupt has sufficient priority. The in-service bits indicate which interrupt requests are being ser-
viced. The priority structure determines whether a new interrupt request’s level has sufficient pri-
ority to interrupt the current process.
You can use one of three methods to clear an in-service bit: enable the automatic end-of-interrupt
(AEOI) mode, issue a specific end-of-interrupt (EOI) command, or issue a nonspecific EOI com-
mand. The AEOI mode is available only on the master 82C59A.
AEOI mode This mode is enabled during system initialization. In
this mode, the 82C59A clears the in-service bit at the
beginning of an interrupt’s processing. This means
that interrupts of any level can interrupt the
processing of other interrupts.
Specific EOI command This command instructs the 82C59A to clear a
specific IR in-service bit.
Nonspecific EOI command This command instructs the 82C59A to clear the in-
service bit that corresponds to the highest level IR
signal active at that time.