Intel 386 - Manual (Page 5)

Intel386™ EX MICROPROCESSOR USER’S MANUAL
iv
4.5.2 Enabling and Disabling the Expanded I/O Space .....................................................4-8
4.5.2.1 Programming REMAPCFG Example ...................................................................4-8
4.6 ADDRESSING MODES ................................................................................................. 4-9
4.6.1 DOS-compatible Mode ..............................................................................................4-9
4.6.2 Nonintrusive DOS Mode .........................................................................................4-11
4.6.3 Enhanced DOS Mode .............................................................................................4-11
4.6.4 Non-DOS Mode ......................................................................................................4-11
4.7 PERIPHERAL REGISTER ADDRESSES.................................................................... 4-15
CHAPTER 5
DEVICE CONFIGURATION
5.1 INTRODUCTION ........................................................................................................... 5-1
5.2 PERIPHERAL CONFIGURATION ................................................................................. 5-3
5.2.1 DMA Controller, Bus Arbiter, and Refresh Unit Configuration ..................................5-3
5.2.1.1 Using The DMA Unit with External Devices .........................................................5-3
5.2.1.2 DMA Service to an SIO or SSIO Peripheral .........................................................5-3
5.2.1.3 Using The Timer To Initiate DMA Transfers .........................................................5-4
5.2.1.4 Limitations Due To Pin Signal Multiplexing ..........................................................5-4
5.2.2 Interrupt Control Unit Configuration ..........................................................................5-7
5.2.3 Timer/counter Unit Configuration ............................................................................5-11
5.2.4 Asynchronous Serial I/O Configuration ...................................................................5-14
5.2.5 Synchronous Serial I/O Configuration ....................................................................5-18
5.2.6 Chip-select Unit and Clock and Power Management Unit Configuration ................5-19
5.2.7 Core Configuration ..................................................................................................5-21
5.3 PIN CONFIGURATION................................................................................................ 5-23
5.4 DEVICE CONFIGURATION PROCEDURE ................................................................ 5-28
5.5 CONFIGURATION EXAMPLE..................................................................................... 5-28
5.5.1 Example Design Requirements ...............................................................................5-28
5.5.2 Example Design Solution ........................................................................................5-29
CHAPTER 6
BUS INTERFACE UNIT
6.1 OVERVIEW ................................................................................................................... 6-1
6.1.1 Bus Signal Descriptions ............................................................................................6-3
6.2 BUS OPERATION ......................................................................................................... 6-5
6.2.1 Bus States .................................................................................................................6-7
6.2.2 Pipelining ..................................................................................................................6-8
6.2.3 Data Bus Transfers and Operand Alignment ............................................................6-9
6.2.4 Ready Logic ............................................................................................................6-10
6.3 BUS CYCLES .............................................................................................................. 6-13
6.3.1 Read Cycle .............................................................................................................6-13
6.3.2 Write Cycle ..............................................................................................................6-16
6.3.3 Pipelined Cycle .......................................................................................................6-19