Intel 386 - Manual (Page 128)

6-15
BUS INTERFACE UNIT
Figure 6-5. Nonpipelined Address Read Cycles
A2487-03
LOCK#
D15:0
CLK2
BHE#, BLE#, A25:1
M/IO#, D/C#
Valid1
RD#
READY#
Ti T1 T2 T1 T2 T2 Ti
Cycle 1
Non-pipelined
External
(Read)
Cycle 2
Non-pipelined
External
(Read)
Idle
CLKOUT
Idle
ADS#
NA#
REFRESH#
W/R#
End Cycle End Cycle
In1 In2
WR#
LBA#
BS8#
Valid2
Valid1 Valid2