Intel 386 - Manual (Page 545)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
B-4
the Intel386 EX embedded processor) demonstrates the design of a Synchronous Expansion Bus
that is very similar to the ISA bus. The Intel386 EX processor is not capable of providing a 100%
compatible ISA bus due to its lack of DMA channels and interrupt inputs.
B.1.3 Interrupt Control Unit
Interrupt signals IRQ10, IRQ11, and IRQ15 found on an ISA bus are not directly available for
external interrupt connections in systems based on an Intel386 EX processor. If an application
intends to use these IRQn signals, then they can be rerouted to other IRQ signals available in an
Intel386 EX processor architecture, and the respective interrupt handler routines assigned accord-
ingly.
B.1.4 SIO Units
In the modem control register (MCR), the OUT1 register bit is used only in loopback tests. The
OUT2 bit in the MCR is used as an SIO interrupt enable control signal. This allows two additional
UARTs to be added externally as COM3 and COM4.
The SIO units (COM1 and COM2) are connected to the equivalent of a PC’s local bus, not the
ISA bus. However, this does not affect the compatibility with DOS application software in any
form.
B.1.5 CPU-only Reset
The RESET pin on the Intel386 EX processor can be considered to function as a system reset
function because all of the on-chip peripheral units, as well as the CPU core, are initialized to a
known start-up state. There is no separate reset pin that goes only to the CPU. Some CPU-only
reset modes, such as a keyboard controller generated CPU-only reset, will not function as expect-
ed.
A CPU-only reset can be implemented by routing the reset signal to either the NMI or SMI# sig-
nal, and the appropriate handler code could then generate a corresponding CPU-Only-Reset func-
tion by setting bit 0 of the PORT92H register.
B.1.6 HOLD, HLDA Pins
These pins do not connect directly to the CPU. Instead they go to the Bus Arbiter which controls
the internal HOLD and HLDA signals connected to the CPU core. However the presence of the
bus arbiter is transparent as far as functionality of the external HOLD and HLDA pins of Intel386
EX processor are concerned.
In a PC/AT system, if an external bus master gains the bus by raising HOLD to the CPU or raising
DREQ in DMA cascade mode, the corresponding HLDA or DACK signal stays active until the
bus master drops HOLD or DREQ. In the Intel386 EX processor, when the refresh control unit
requests the bus, the bus arbiter deactivates the signals on the HLDA or DACK# pins while the
external bus master still has the bus (HOLD or DREQ is high). At this point, the external bus mas-
ter or DMA must deassert its HOLD or DREQ signal for a minimum of one CPU clock cycle and
it can then assert the signal again.