Intel 386 - Manual (Page 662)

E-25
INSTRUCTION SET SUMMARY
E.2.2.3 Encoding of the Segment Register (sreg) Field
The sreg field in certain instructions is a 2-bit field allowing one of the four 80286 segment reg-
isters to be specified. The sreg field in other instructions is a 3-bit field, allowing the FS and GS
segment registers to be specified.
Table E-5. Encoding of reg Field When w Field is Present in Instruction
Register Specified by reg Field During 16-bit Data Operations
reg
Function of w Field
(when w = 0) (when w = 1)
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AH
CH
DH
BH
AX
CX
DX
BX
SP
BP
SI
DI
Register Specified by reg Field During 32-bit Data Operations
reg
Function of w Field
(when w = 0) (when w = 1)
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AH
CH
DH
BH
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
Table E-6. Encoding of the Segment Register (sreg) Field
2-Bit sreg2
Field
Segment Register Selected
3-Bit sreg3
Field
Segment Register Selected
00
01
10
11
ES
CS
SS
DS 000
001
010
011
100
101
110
111
ES
CS
SS
DS
FS
GS
do not use
do not use