Intel 386 - Manual (Page 523)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
18-10
18.3 TESTING
This section explains how to use the test-logic unit to test the device and the board interconnec-
tions. For any test, you must load an instruction and perform an instruction-scan cycle, then sup-
ply the correct sequence of ones and zeros to move the TAP controller through the required states
to perform the test.
18.3.1 Identifying the Device
The IDCODE instruction allows you to determine the contents of a device’s IDCODE register.
When TRST# is asserted, the test-logic-reset state forces the IDCODE instruction into the in-
struction register’s parallel output latches. You can also load this instruction like any other, by ma-
nipulating the TDI input to supply the binary opcode (0010). The Capture-DR state loads the
identification code into the IDCODE register, and the Shift-DR state shifts the value out.
18.3.2 Bypassing Devices on a Board
The BYPASS instruction allows you to bypass one or more devices on a board while testing oth-
ers. This significantly reduces the time required for a test. For example, assume that a board has
100 devices, each of which has 101 bits in its boundary-scan register. If the boundary-scan cells
are all connected in series, the boundary-scan path is 10,100 stages long. Bypassing devices al-
lows you to shorten the path considerably. If you set 99 of the devices to shift through their bypass
registers and only a single chip to shift through its boundary-scan register (101 bits in this case),
the serial path is only 200 stages long.
You load the BYPASS instruction by manipulating TDI to supply the binary opcode (1111). The
Capture-DR state loads a logic 0 into the bypass register and the Shift-DR state shifts the value
out.
18.3.3 Sampling Device Operation and Preloading Data
The SAMPLE/PRELOAD instruction has two functions: SAMPLE takes a snapshot of data flow-
ing from (or to) the system pins to (or from) on-chip system logic, while PRELOAD places an
initial data pattern at the latched parallel outputs of the boundary-scan register cells in preparation
for another boundary-scan test operation.
You load the SAMPLE/PRELOAD instruction by manipulating TDI to supply the binary opcode
(0001). The Shift-DR state places the boundary-scan register in the serial path between TDI and
TDO, the Capture-DR state loads the pin states into the boundary-scan register, and the Update-
DR state loads the shift-register contents into the boundary-scan register’s parallel outputs.
18.3.4 Testing the Interconnections (EXTEST)
The EXTEST instruction allows testing of off-chip circuitry and board-level interconnections.
Boundary-scan cells at the system outputs are used to apply test stimuli, while cells at system in-
puts capture the results. The Capture-DR state captures input pins into the chain; the Update-DR
state drives the new values of the parallel output onto the output pins.