Intel 386 - Manual (Page 606)

D-41
SYSTEM REGISTER QUICK REFERENCE
D.38 OCW2 (MASTER AND SLAVE)
Operation Command Word 2
OCW2 (master and slave)
(write only)
Expanded Addr:
ISA Addr:
Reset State:
master slave
F020H F0A0H
0020H 00A0H
XXH XXH
7 0
R SL EOI RSEL1 RSEL0 L2 L1 L0
Bit
Number
Bit
Mnemonic
Function
7 R The Rotate (R), Specific Level (SL), and End-of-Interrupt (EOI) Bits:
These bits change the priority structure and/or send an EOI command.
R SL EOI Command
0 0 0 Cancel automatic rotation*
0 0 1 Send a nonspecific EOI command
0 1 0 No operation
0 1 1 Send a specific EOI command**
1 0 0 Enable automatic rotation*
1 0 1 Enable automatic rotation and send a nonspecific EOI
1 1 0 Initiate specific rotation**
1 1 1 Initiate specific rotation and send a specific EOI**
* These cases allow you to change the priority structure while the
82C59A is operating in the automatic EOI mode.
** The L2:0 bits (see below) specify the specific level for these cases.
6 SL
5 EOI
4–3 RSEL1:0 Register Select Bits:
ICW1, OCW2 and OCW3 are accessed through the same addresses.
The states of RSEL1:0 determine which register is accessed. Write 00
to these bits to access OCW2.
RSEL1 RSEL0
0 0 OCW2
0 1 OCW3
1 X ICW1
2–0 L2:0 IR Level:
When you program bits 7–5 to initiate specific rotation, these bits specify
the IR signal that is assigned the lowest level.
When you program bits 7–5 to send a specific EOI command, these bits
specify the IR signal that receives the EOI command.
If SL=0, then these bits have no effect.