Intel 386 - Manual (Page 149)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
6-36
6.5.1 HOLD/HLDA Timing
To gain control of the local bus, the requesting bus master drives the HOLD input active. This
signal can be asynchronous to the processor’s CLK2 input. The processor responds by:
• completing its current bus cycle
• deasserting WR#, RD#, LBA#, SMIACT#, UCS#, CS6:0# and REFRESH# and three-
stating all other bus outputs except HLDA (effectively removing itself from the bus)
• driving HLDA active to signal the requesting bus master that it may take control of the bus
The requesting bus master must maintain HOLD active until it no longer needs the bus. When
HOLD goes low, the processor drives HLDA low and starts a bus cycle (if one is pending).
For valid system operation, the requesting bus master must not take control of the bus until it re-
ceives the HLDA signal and must remove itself from the bus before deasserting the HOLD signal.
Setup and hold times relative to CLK2 for both rising and falling transitions of the HOLD signal
must be met.
If the internal refresh control unit is used, the HLDA signal may drop while an external master
has control of the bus, in which case the external bus master may or may not drop HOLD to allow
the processor to perform the refresh cycle. If the latter occurs, the memory device(s) may lose
data because the refresh cycle could not execute.
When the processor receives an active HOLD input, it completes the current bus cycle before re-
linquishing control of the bus. Figure 6-7 shows the state diagram for the bus including the HOLD
state.
During HOLD, the processor can continue executing instructions that are already in its prefetch
queue. Program execution is delayed if a read cycle is needed while the processor is in the HOLD
state. The processor can queue one write cycle internally, pending the return of bus access; if more
than one write cycle is needed, program execution is delayed until HOLD is released and the pro-
cessor regains control of the bus.
HOLD has priority over most core bus cycles, but is not recognized under certain conditions:
• During locked cycles
• Between two interrupt acknowledge cycles (LOCK# asserted)
• During misaligned word transfers (LOCK# not asserted)
• During doubleword (32-bit) transfers (LOCK# not asserted)
• During misaligned doubleword transfers (LOCK# not asserted)
• During an active RESET signal (HOLD is recognized during the time between the falling
edge of RESET and the first instruction fetch)
All inputs are ignored while the processor is in the HOLD state, except for the following:
• HOLD pin - It is monitored to determine when the processor may regain control of the bus.
• RESET pin - It is of a higher priority than HOLD. An active RESET input reinitializes the
device.