Intel 386 - Manual (Page 161)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
7-2
• SMI# cannot interrupt currently executing SMM code. The processor latches the falling
edge of a pending SMI# signal while the Intel386 EX processor is executing an existing
SMI# (this allows one level of buffering). The nested SMI# is not recognized until after the
execution of a resume instruction (RSM).
• SMI# brings the processor out of idle or powerdown mode.
7.2.2 SMM Active Output (SMIACT#)
This output indicates that the processor is operating in system management mode. It is asserted
when the CPU initiates the SMM sequence and remains active (low) until the processor executes
the RSM instruction (described in “Resume Instruction (RSM)” on page 7-15) to leave SMM. Be-
fore SMIACT# is asserted, the CPU waits until the end of the instruction boundary. SMIACT# is
used to establish a new memory map for SMM operation. The processor supports this function
by an extension to the internal chip-select unit. In addition, external logic can use this pin to qual-
ify RESET and SMI#. SMIACT# never transitions during a pipelined bus cycle.
7.2.3 System Management RAM (SMRAM)
The SMM architecture requires that a partition of memory be set aside for the SMM driver. This
is called the SMRAM. Several requirements must be met by the system:
• The address range of this partition must be, as a minimum, from 038000H to 03FFFFH
(32 Kbytes).
• The address range from 03FE00H to 03FFFFH (512 bytes) is reserved for the CPU and
must be RAM.
• The SMM handler must start execution at location 038000H. It is not relocatable.
• During normal operation the SMRAM is only accessible when the system is in SMM.
• During system initialization it must be possible to access the SMRAM in order to initialize
it and possibly to install the SMM driver. Obviously, this must be done outside of SMM.
• When the SMRAM overlays other memory in the system, then address decoding and chip
selects must allow the SMM driver to access the shadowed memory locations while in
SMM.
• The SMRAM should not be accessible to alternate bus masters such as DMA.
These requirements are made to ensure that the SMM remains transparent to non-SMM code and
to maintain uniformity across the various Intel processors that support this mode.
NOTE
It is possible for the designer of an embedded system to place the SMM driver
code in read-only storage, as long as the address space between 03FE00H and
03FFFFH is writable.
The Intel386 EX processor does not support SMRAM relocation. Bit 17 of the SMM Revision
Identifier (see “SMRAM State Dump Area” on page 7-14) indicates whether the processor sup-