Figure 56. timer/counter unit configuration – Intel 386 User Manual

Page 85

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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

5-12

Figure 5-6. Timer/Counter Unit Configuration

A2517-03

CLKIN0

GATE0

OUT0

GATE1

Timer/Counter

Unit

CLKIN1

OUT1

GATE2

CLKIN2

OUT2

0

1

TMROUT0
(INT9)
(P3.0)

To/From I/O Port 3

P3CFG.0

TMRCLK0
(INT4)

PSCLK

TMRCFG.7

TMRCFG.0

To ICU

To ICU

0

1

TMRCLK1
(INT6)

PSCLK

TMRCFG.2

To ICU

TMROUT1
(INT8)
(P3.1)

To/From I/O Port 3

P3CFG.1

To ICU, DMA

0

1

TMRCLK2
(PEREQ)

PSCLK

TMRCFG.4

To Core

0

1

TMRGATE2
(BUSY#)

V

CC

TMRCFG.6

TMRCFG.5

PINCFG.5

TMROUT2
(ERROR#)

To Core

To ICU, DMA

Alternate pin signals are in parentheses.

0

1

To Core

TMRCFG.5

0

1

TMRGATE1
(INT7)

V

CC

TMRCFG.6

TMRCFG.3

1

To ICU

TMRCFG.3

0

0

1

TMRGATE0
(INT5)

V

CC

TMRCFG.6

TMRCFG.1

1

To ICU

TMRCFG.1

0

1

0

1

0

1

0

1

0

1

0

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