Intel 386 - Manual (Page 236)

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INTERRUPT CONTROL UNIT
#define IR7 0x80
Disable8259Interrupt(IR0 | IR1 | IR3 | IR4 | IR5 | IR6 | IR7,
IR1 | IR2 | IR3 | IR4 |IR5 | IR6);
Real/Protected Mode
No changes required.
*****************************************************************************/
void Disable8259Interrupt(BYTE MstrMask, BYTE SlaveMask)
{
BYTE Mask;
if(MstrMask != 0)
{
Mask = _GetEXRegByte(OCW1M);
_SetEXRegByte(OCW1M, Mask | MstrMask);
}
if(SlaveMask != 0)
{
Mask = _GetEXRegByte(OCW1S);
_SetEXRegByte(OCW1S, Mask | SlaveMask);
}
}/* Disable8259Interrupt */
/*****************************************************************************
Enable8259Interrupt:
Description:
Enables 8259a interrupts for the master and the slave.
Parameters:
MstrMask Enable mask value for master ICU
SlaveMask Enable mask value for slave ICU
Each bit location that is set enables the corresponding
interrupt (by clearing the bit in the interrupt control register).
For example, to enable master IR3 and IR5 set MstrMask = 0x28
(bits 3 and 5 are set).
Returns:
None
Assumptions:
REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
Syntax: